The present invention relates to a semiconductor memory structure, and more particularly to a design layout, i.e., arrangement, for a semiconductor memory structure which includes a double wiggled wordline offset that increases the effective channel length of the array device without constricting the area for the capacitor contacts as is typically the case with prior art wiggled wordline arrangements. In the present invention, various offsets are employed to achieve maximized channel length, while maintaining maximized contact areas for the bitline contacts and the capacitor contacts.
In semiconductor memory device manufacturing, the channel length of the DRAM (dynamic random access memory) transfer gate devices continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for low leakage DRAM transfer devices. There is thus a need for novel cell layouts which provide only limited shrinking of the channel length.
As the DRAM cell size decreases, the transfer gate (i.e., gate polysilicon) has consequently shrunk with it. Earlier cell sizes ( greater than 8F2) allow for wiggled gates to keep the array transistor xe2x80x98offxe2x80x99 leakage to a minimum. With the onset of 8F2 and other denser memory cells with equal lines and spaces at minimum feature size, F, in the wordline direction, there is need to provide larger gate lengths of the array transistors so as to ensure retention of stored data. Large gate lengths are especially required to allow for using a xe2x80x9chardxe2x80x9d device turnoff. With small gate lengths, a hard turnoff oftentimes results in some loss of stored information. In contrast, larger gate lengths prevent loss of data during a hard device turnoff.
A typical prior art design layout for a sub-8F2 memory cell is shown in FIG. 1. Specifically, FIG. 1 is a top view of a prior art 6F2 memory cell which includes vertical bitlines 10, horizontal wordlines 12, capacitor contacts 14, bitline contacts 16, and active (diffusion) areas 18 that include a source region and a drain region. As shown in FIG. 1, the distance between each wordline is 1F, whereas the distance between each bitline is 2F.
Reference is now made to the top, right hand corner of FIG. 1 in which the distances between 4 neighboring contacts (labeled as A, B, C and D, respectively) are shown. It should be noted that the distance between AB represents the channel length of the gate polysilicon on the active area of the layout, while the distance DC represents the length of the wordline on an isolation region. An expanded view of this region of the prior art layout is shown in FIG. 2. As is shown in FIG. 2, the distance between contacts represented as AB, CD, AC is the same and is approximately 2.24 F. However, the distance between contacts BC and DA is only about 2F.
The prior art structure shown in FIGS. 1-2 exhibits short channel effects because of the 1F nominal channel length. For improved device performance, channel length AB needs to be maximized and the distances between any contact needs to be the same.
To maximize the gate length AB, wiggled wordline design layouts, such as shown in FIG. 3, are typically employed. In the wiggled wordline design of prior art structures, the wordlines are made to jog about the various contact regions of the memory cells. Despite obtaining maximum gate lengths on the active areas and maximum contact areas for bitline contacts, prior art wiggled wordline design layouts do not achieve maximum contact area for the capacitor contacts. Instead, the contact area of the capacitor contacts in prior art wiggled wordline structures is constricted. Because of this constriction, prior art wiggled wordlines have a high contact resistance associated therewith.
In view of the drawbacks with prior art memory structures, there is a continued need to develop new and improved design layouts for memory cells in which the channel length of the gate conductor on the active areas is maximized, while maintaining maximum contact areas for both the bitline contact and the capacitor contact. Such a design layout would be extremely beneficial since it would result in a memory structure having improved operation properties as compared to prior art wiggled wordline designs.
One object of the present invention is to provide a design layout for a dense memory cell (sub-8F2) structure that achieves a maximized gate conductor channel length so as to permit the array device to be turned off xe2x80x98hardxe2x80x99 without the loss of any stored data.
A further object of the present invention is to provide a design layout for a memory cell structure wherein increased channel lengths can be achieved on the active areas of the structure without loss of capacitor contact area.
A still further object of the present invention is to provide a design layout for a memory cell structure wherein increased channel lengths can be achieved, while maintaining maximum contact area for the bitline contacts and capacitor contacts.
An even further object of the present invention is to provide a design layout for a dense memory cell that results in a structure having improved operational properties associated therewith.
These and other objects and advantages are achieved in the present invention by utilizing multiple offsets in the wordline to enable the connection of the bitline contacts and capacitor contacts to the diffusion regions in the substrate. The unique offsets employed in the present invention include a conventional wiggled wordline offset which is used to maximize channel length of the array device on the active areas and to permit maximum contact area for the bitline contact, and additional offsets which provide maximum contact area for both the capacitor and the bitline diffusion contacts.
The combination of offsets employed in the present invention is referred to herein as a xe2x80x9cdouble wiggled wordline offsetxe2x80x9d. The standard wordline offset, i.e., wiggled wordline offset of the prior art, allows a maximum contact area for the bitline contacts at the expense of the contact area of the capacitor contact. To overcome this problem, additional offsetting is employed in the present invention to ensure that the distance between neighboring contacts is the same, while the capacitor contacts and bitline contacts on the active areas have a much larger distance than the other contacts.
Specifically, the design layout of the present invention provides a semiconductor memory structure that comprises horizontally arranged wordlines, vertically arranged bitlines, and sub-8F2 memory cells in a semiconductor substrate, said memory cells comprising
a transfer gate transistor having a source region and a drain region formed in said substrate and a gate electrode,
a memory cell stacked storage capacitor,
a wordline conductor portion contacting said gate electrode, said wordline gate conductor portion forming part of one of said wordlines,
a bitline contact to said source region, said bitline contact connecting said source region to one of said bitlines, and
a capacitor contact between said capacitor and said drain region, wherein for at least one of said cells, said bitline contact and said capacitor contact are positioned at a distance from each other greater than from said bitline contact to a closest contact of another of said cells and greater than from said capacitor contact to a closest contact of another of said cells.
In one preferred embodiment of the present invention, the memory cells are 6F2 memory cells.
In yet another preferred embodiment of the present invention, at least one of the wordlines has an average width and said wordline conductor portion has a width greater than the average width.
In above described memory structure, the design layout is such that the channel length of the transfer device is maximized and the contact areas of both the bitline contact and the capacitor contact are maximized. The above-mentioned properties are achieved in the present invention by utilizing a conventional wiggled wordline offset coupled with offsetting one column of capacitor contacts in one direction, while offsetting an alternating column of capacitor contacts in an opposite direction. In the present invention, the capacitor contacts are offset in the vertical direction.